DEFINITY Enterprise Communications Server Release 7
Maintenance for R7r
555-230-126
Issue 4
June 1999
Maintenance Object Repair Procedures
9-1352PROCR (RISC Processor Circuit Pack)
9
Processor Write Buffer Test (#900)
This test verifies that the Write Buffer operates properly on the Processor circuit
pack. Failure of this test is serious. The Processor circuit pack must be replaced
as soon as possible.
2000 ABORT Response to the test request was not received within the allowable time period.
If the system is equipped with the High Reliability or Critical Reliability
Configuration and if the Processor circuit pack is on the standby SPE, this abort
code may indicate that the standby SPE is not responding to the handshake
message. If this is the case, the standby SPE maintenance software may take
up to two minutes to indicate that handshake communication with the standby
SPE is down. The ABORT code will then change to 1339 (standby SPE
unavailable).
1. Retry the command at 1-minute intervals, a maximum of 3 times.
2334 ABORT The hardware mail on the standby Duplication Interface board is not ready to
receive messages.
1. Retry the command at 1-minute intervals, a maximum of 5 times.
FAIL The Processor cannot detect bus parity error conditions.
1. Retry the command.
2. If the test continues to fail, replace the Processor circuit pack.
3. If the test continues to fail after replacing the Process circuit pack, replace
the SYSAM circuit pack. To replace the Processor circuit pack, refer to
Replacing SPE Circuit Packs
in Chapter 5.
PASS The Processor Parity Checker is functional.
Table 9-532. TEST #900 Processor Write Buffer Test
Error
Code
Tes t
Result Description/ Recommendation
100 ABORT The requested test did not complete within the allowable time period.
1. Retry the command.
Continued on next page
Table 9-531. TEST #899 Processor Parity Checker Test — Continued
Error
Code
Tes t
Result Description/ Recommendation
Continued on next page
