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INTERNAL SPECIFICATIONS
71
4.4.2.5 Interrupt enable register (IE)
IE 0A8H EA — ET2 ES ET1 EX1 ET0 EX0
Name Address
MSB LSB
76543210
Bit location Flag Function
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
IE.6
IE.7
EX0
ET0
EX1
ET1
ES
ET2
—
EA
Interrupt control bit for external interrupt 0.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Interrupt control bit for timer interrupt 0.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Interrupt control bit for external interrupt 1 .
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Interrupt control bit for timer interrupt 1 .
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Interrupt control bit for serial port.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Interrupt control bit for timer interrupt 2.
Interrupt disabled when bit is "0".
Interrupt enabled when bit is "1".
Reserved bit. The output data is "1" if the bit is read.
Overall interrupt control bit.
All interrupts are disabled when bit is "0".
All interrupts are enabled/disabled by IE.0 thru IE.5 when bit is "1".