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163
Table 4-26 CPU pin details (ALF=0) in hard power down mode (HPD)
Name Internal ROM External ROM
P1.0/T2 Port data output Port data output
P1.1/T2EX Port data output Port data output
P1.2 Port data output Port data output
P1.3 Port data output Port data output
P1.4 Port data output Port data output
P1.5 Port data output Port data output
P1.6 Port data output Port data output
P1.7 Port data output Port data output
RESET “0” level input “0” level input
P3.0/RXD Port data output Port data output
P3.1/TXD Port data output Port data output
P3.2/INT0 Port data output Port data output
P3.3/INT1 Port data output Port data output
P3.4/ T0 Port data output Port data output
P3.5/ T1/HPDI “0” level input “0” level input
P3.6/ WR Port data output Port data output
P3.7/RD Port data output Port data output
XTAL 2 Oscillator operative Oscillator operative
XTAL 1 Oscillator operative Oscillator operative
V
SS 0 [V] 0 [V]
P2.0 Port data output Port data output
P2.1 Port data output Port data output
P2.2 Port data output Port data output
P2.3 Port data output Port data output
P2.4 Port data output Port data output
P2.5 Port data output Port data output
P2.6 Port data output Port data output
P2.7 Port data output Port data output
PSEN “0” level output “0” level output
ALE “0” level output “0” level output
EA “1” level input “0” level input
P0.7 Port data output Floating
P0.6 Port data output Floating
P0.5 Port data output Floating
P0.4 Port data output Floating
P0.3 Port data output Floating
P0.2 Port data output Floating
P0.1 Port data output Floating
P0.0 Port data output Floating
V
CC *+2.0~+6 [V] *+2.0~+6 [V]
* V
CC=+2.0~+6V when internal CPU data is held.