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DESCRIPTION OF INSTRUCTIONS
237
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Byte Cycle Description Page
Classifi-
cation
Immediate data
setting instructions
Logical operation instructions
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
MOV
MOV
MOV
A, #data
direct, A
direct,#data
A, Rr
A, direct
A, @Rr
A, #data
direct, A
direct,#data
A, #data
Rr, #data
direct, #data
2
2
3
1
2
1
2
2
3
2
2
3
1
1
2
1
1
1
1
1
2
1
1
2
(A)←(A)OR#data
(direct address)←(direct address)OR(A)
(direct address)←(direct address)OR#data
(A)←(A)XOR(Rr) r=0~7
(A)←(A)XOR(direct address)
(A)←(A)XOR((Rr)) r=0 or 1
(A)←(A)XOR#data
(direct address)←(direct address)XOR(A)
(direct address)←(direct address)XOR#data
(A)←#data
(Rr)←#data r=0~7
(direct address)←#data
337
344
343
368
369
367
366
371
370
314
320
324
01000100
I
7 I6 I5 I4 I3 I2 I1 I0
01000010
a
7 a6 a5 a4 a3 a2 a1 a0
01000011
a
7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
01101r2 r1 r0
01100101
a
7 a6 a5 a4 a3 a2 a1 a0
0110011r
01100100
I
7 I6 I5 I4 I3 I2 I1 I0
01100010
a
7 a6 a5 a4 a3 a2 a1 a0
01100011
a
7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
01110100
I
7 I6 I5 I4 I3 I2 I1 I0
01111r2 r1 r0
I7 I6 I5 I4 I3 I2 I1 I0
01110101
a
7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0