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MSM80C154S/83C154S/85C154HVS
236
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Byte Cycle Description Page
Classifi-
cation
Increment & decrement instructions Logical operation instructions
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
ANL
ANL
ANL
ANL
ANL
ANL
ORL
ORL
ORL
A
Rr
direct
@Rr
DPTR
A
Rr
direct
@Rr
A, Rr
A, direct
A, @Rr
A, #data
direct, A
direct,#data
A, Rr
A, direct
A, @Rr
1
1
2
1
1
1
1
2
1
1
2
1
2
2
3
1
2
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
2
1
1
1
(A)←(A)+1
(Rr)←(Rr)+1 r=0~7
(direct address)←(direct address)+1
((Rr))←((Rr))+1 r=0 or 1
(DPTR)←(DPTR)+1
(A)←(A)–1
(Rr)←(Rr)–1 r=0~7
(direct address)←(direct address)–1
((Rr))←((Rr))–1 r=0 or 1
(A)←(A)AND(Rr) r=0~7
(A)←(A)AND(direct address)
(A)←(A)AND((Rr)) r=0 or 1
(A)←(A)AND#data
(direct address)←(direct address)AND(A)
(direct address)←(direct address)AND#data
(A)←(A)OR(Rr) r=0~7
(A)←(A)OR(direct address)
(A)←(A)OR((Rr)) r=0 or 1
290
292
293
289
291
281
282
283
280
258
259
257
256
263
262
339
340
338
00000100
00001r
2 r1 r0
00000101
a
7 a6 a5 a4 a3 a2 a1 a0
0000011r
10100011
00010100
00011r
2 r1 r0
00010101
a
7 a6 a5 a4 a3 a2 a1 a0
0001011r
01011r
2 r1 r0
01010101
a
7 a6 a5 a4 a3 a2 a1 a0
0101011r
01010100
I
7 I6 I5 I4 I3 I2 I1 I0
01010010
a
7 a6 a5 a4 a3 a2 a1 a0
01010011
a
7 a6 a5 a4 a3 a2 a1 a0
I7 I6 I5 I4 I3 I2 I1 I0
01001r2 r1 r0
01000101
a
7 a6 a5 a4 a3 a2 a1 a0
0100011r