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MSM80C154S/83C154S/85C154HVS
234
7.4 Simplified Description of Instructions
Note that “data address” is represented as “direct address” in this description.
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Byte Cycle Description Page
Classifi-
cation
Arithmetic operation instructions
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
SUBB
SUBB
SUBB
SUBB
MUL
DIV
DA
A, Rr
A, direct
A, @Rr
A, #data
A, Rr
A, direct
A, @Rr
A, #data
A, Rr
A, direct
A, @Rr
A, #data
AB
AB
A
00101r2 r1 r0 1
2
1
2
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
1
(AC),(OV),(C),(A)
←
(A)+(Rr) r=0~7
(AC),(OV),(C),(A)
←
(A)+(direct address)
(AC),(OV),(C),(A)
←
(A)+((Rr)) r=0 or 1
(AC),(OV),(C),(A)
←
(A)+#data
(AC),(OV),(C),(A)
←
(A)+(C)+(Rr) r=0~7
(AC),(OV),(C),(A)
←
(A)+(C)+(direct address)
(AC),(OV),(C),(A)
←
(A)+(C)+((Rr)) r=0 or 1
(AC),(OV),(C),(A)
←
(A)+(C)+#data
(AC),(OV),(C),(A)
←
(A)–((C)+(Rr)) r=0~7
(AC),(OV),(C),(A)
←
(A)–((C)+(direct address))
(AC),(OV),(C),(A)
←
(A)–((C)+((Rr))) r=0 or 1
(AC),(OV),(C),(A)
←
(A)–((C)+#data)
(AB)
←
(A)
×
(B)
(A) quotient, (B) remainder
←
(A)
/
(B)
When the contents of accumulator bit 0 thru 3 exceed
9, and when the auxiliary carry (AC) is 1, 6 is added to
bits 0 thru 3. And if examination od bits 4 thru 7 shows
that the result of adding the carry following correction of
the lower order bits 0 thru 3 by 6 is in excess of 9, or
carry (C) is 1, 6 is added to bits 4 thru 7. If a carry is
generated as a result, 1 is set in the carry flag.
249
250
248
247
253
254
252
251
359
360
358
357
335
284
278
00100101
a
7 a6 a5 a4 a3 a2 a1 a0
0010011r
00100100
I
7 I6 I5 I4 I3 I2 I1 I0
00111r2 r1 r0
00110101
a
7 a6 a5 a4 a3 a2 a1 a0
0011011r
00110100
I
7 I6 I5 I4 I3 I2 I1 I0
10011r2 r1 r0
10010101
a
7 a6 a5 a4 a3 a2 a1 a0
1001011r
10010100
I
7 I6 I5 I4 I3 I2 I1 I0
10100100
10000100
11010100