Filter
Top Products
CONTENTS
1. INTRODUCTION
1.1 MSM80C154S/MSM83C154S/MSM85C154HVS Outline ..................................3
1.2 MSM80C154S/MSM83C154S Features .............................................................5
1.3 Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS ...........7
2. SYSTEM CONFIGURATION
2.1 MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols ....................11
2.2 MSM80C154S/MSM83C154S Pin Layout ........................................................12
2.2.1 MSM80C154S/MSM83C154S external dimensions ..................................15
2.2.2 MSM85C154HVS pin layout and external dimensions ..............................17
2.3 MSM80C154S Block Diagram ..........................................................................18
2.4 MSM83C154S Block Diagram ..........................................................................19
2.5 MSM85C154HVS Block Diagram .....................................................................20
2.6 Timing and Control ...........................................................................................21
2.6.1 Outline of MSM80C154S/MSM83C154S timing ........................................21
2.6.2 Major synchronizing signals ......................................................................23
(1) ALE ......................................................................................................23
(2) PSEN ...................................................................................................23
(3) WR ...................................................................................................... 23
(4) RD ....................................................................................................... 23
2.6.3 MSM80C154S fundamental operation time charts ....................................24
(1) External program memory read cycle timing chart...............................24
(2) MOVX A, @Rr ......................................................................................24
(3) MOVX @Rr, A ......................................................................................25
(4) MOVX A, @DPTR ................................................................................25
(5) MOVX @DPTR, A ................................................................................26
(6) MOV direct, PORT[0, 1, 2, 3] execution ...............................................26
2.6.4 MSM83C154S fundamental operation time charts ....................................27
(1) MOVX A, @Rr ......................................................................................27
(2) MOVX @Rr, A ..................................................................................... 27
(3) MOVX A, @DPTR ................................................................................28
(4) MOVX @DPTR, A ................................................................................28
(5) MOV direct, PORT[0, 1, 2, 3] execution ...............................................29
2.7 Instruction Register (IR) and Instruction Decoder (PLA) ..................................30
2.8 Arithmetic Operation Section ............................................................................31
(1) Outline ..................................................................................................31
(2) Arithmetic operation instruction decoder ..............................................31
(3) Arithmetic and logic unit (ALU).............................................................31
2.9 Program Counter ..............................................................................................32
2.10 Program Memory and External Data Memory ..................................................33
2.10.1 MSM80C154S/MSM83C154S program area and
external ROM connections ........................................................................33
2.10.2 Procedures and circuit connections used when external
data memory (RAM) is accessed by data pointer (DPTR) ........................35
2.10.3 Procedures and circuit connections used when external
data memory (RAM) is accessed by registers R0 and R1.........................38