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DESCRIPTION OF INSTRUCTIONS
365
105. XCHD A, @Rr (Exchange low nibbles of indirect address with accumulator)
1101011r
70
Instruction code
Operation
Number of bytes
Number of cycles
Flags
(PSW)
Description
Example XCHD A, @R0
Instruction code
: Byte 1
(A
0~3)
←
→
((Rr0~3)) r=0 or 1:
C AC F0 RS1 RS0 OV F1 P
•
:
:
:
The lower order bits (0 thru 3) of the accumulator contents are
exchanged with contents of the lower order bits (0 thru 3) of the
data memory location addressed by the register r contents. The
flag is updated.
:
11010110
70
Byte 1
Accumulator
11110110
70
1
1
Before execution
Accumulator
11111101
70
After execution
:
Register 0
01100000
70
Register 0
01100000
70
60H
00001101
70
60H
00000110
70