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MSM80C154S/83C154S/85C154HVS
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4.6.3.2.5 Mode 1 UART error detection
If the following two conditions are satisfied when the hexadecimal counter is in state 10 during
reception of the stop bit, it is assumed that new data is received before processing of the
previously received data has been completed. Hence, an overrun error is generated, and the
new data is lost. The SERR flag is set at the first M1·S3 after the hexadecimal counter has
reached state 10. Note that the previous SBUF (R) data is preserved.
Conditions: (1) RI=“1”
(2) SM2=“0”, or SM2=“1” and sampled stop bit=“1”
And if the sampled stop bit is “0” when the hexadecimal counter is in state 10, it is assumed
that correct frame synchronization has not been achieved. Hence, a framing error is detected,
and the SERR flag is set at the first M1·S3 after that. Serial port reception is not effected by
the UART error detector circuit detecting an overrun or framing error and only the status flag
being set.