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Chapter 3: Programming the Peripherals
4538 Hardware Reference Manual 77
NOTE
For T1/J1 applications, the mapping of the receive 24 line time slots over the 32
available on the system interface is configurable with FMR1.CTM bit. In 4538 Boot
firmware, the choice is to select ‘Channel translation mode 1’, by setting FRM1.CTM
bit to 1: on reception, the 24 line time slots are contiguously mapped before they are
interleaved on the system bus. The same mapping occurs on transmission.
RCLK1 Configuration as TDM Bus Clock
See Boot Firmware sources: tst\c\qfalc.c - Function gvQFalcSetPortSyncSrc.
RCLK1 signal of QuadFALC is recovered from the line and dejittered by DCO-R. It must
be configured as an active output (PC5.CRP = 1). RCLK2, RCLK3, and RCLK4 shall be
configured as inputs (PC5.CRP = 0).
RCLK1 is one of the four channels’ internally generated receive route clocks (RCLK) (a
channel is a FALC within a QuadFALC) of a QuadFALC: the channel selection is set with
GPC1.R1S1 and GPC1.R1S0 bits – when using RCLK1 for synchronizing the TDM
SIxRAM, an active channel should be selected. On each channel, program CMR1.RS1=1
and CMR1.RS0=1: the advantage would be to have RCLK1 at 8.192 MHz whatever the
source’s channel mode is (T1/J1 or E1), the disadvantage is that in case of an LOS (Loss
Of Signal) on the source channel, RCLK1 does not go to a continuous level, but is the free
running frequency of DCO-R. Since DCO-R is used, program CMR1.DRSS1 and
CMR.DRSS0 bits as shown in Table 3-3 to select the reference source for the DCO-R
circuit.
Table 3-2. Channel Phase Programming in Multiplexed System Data Streams
Channel SIC2.SICS2...0
Table 3-3. QuadFALC RCLK Reference Source for DCO-R
Channel CMR1.DRSS1 CMR1.DRSS0