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Chapter 3: Programming the Peripherals
4538 Hardware Reference Manual 81
not go to a continuous level, but is the free running frequency of DCO-R. Since DCO-R is
used, program CMR1.DRSS1 and CMR.DRSS0 bits as shown in Table 3-3 to select the
reference source for the DCO-R circuit
SEC/FSC Configuration
The SEC/FSC signal of the QuadFALC is connected to CPM and is used for the TDM frame
synchronization clock (8 KHz synchronization pulse generated by one of the four DCO-R).
It must be configured as an FSC output by setting GPC1.CSFP1 to 1. Bit GPC1.CSFP0
allows selecting the active level (low or high). When using the pairing feature, FSC source
must match an active channel as for RCLK1: the source is selected with GPC1.FSS1 and
GPC1.FSS0 bits.
See Boot Firmware sources: TST\C\QFALC.C Function gvQFalcSetPortSyncSrc.