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Chapter 1: Hardware Description
4538 Hardware Reference Manual 31
The QuadFALC includes a flexible clock unit that uses a clock supplied on its MCLK pin.
The QuadFALC MCLK input is connected to a 12.500 MHz +/-20ppm fixed frequency
(CPM BRG6) used by the internal DPLL. As a result, the GCM registers must be
programmed with the following values:
The QuadFALC has an integrated short-haul and long-haul line interface, comprising a
receive equalization network, noise filtering, and programmable Line Build-Outs (LBOs).
It implements an integrated Channel Service Unit (CSU) in T1 mode. For each type of
LBO, the shape of the transmit pulse must be adjusted through its registers LIM0, LIM2,
XPM0, XPM1, and XPM2 in order to comply with FCC 68 or ANSI T1.403. Table 1-27
provides the values in T1 mode for the 4538 hardware (in E1 mode, default values are
suitable)
Table 1-26. GCM Register Programming (MCLK=12.500 MHz)
Register Value
*&0 [%
*&0 ['
*&0 [$&
*&0 [
*&0 [
*&0 [
Table 1-27. Transmit Pulse Shape Programming
Line Build-Out LIM0:EQON LIM2:LBO2–1
2 Front Access 4 Rear Access
XPM0 XPM1 XPM2 XPM0 XPM1 XPM2
(6KRUW+DXO
±
[ [ [ [& [ [
(/RQJ+DXO
±
[ [ [ [& [ [
76KRUW+DXOQR&68 [' [$ [ [%) [$ [
7/RQJ+DXOG% [' [$ [ [%) [$ [
7/RQJ+DXO
±G% [) [ [ [) [ [
7/RQJ+DXO
±G% [% [ [ [% [ [
7/RQJ+DXO
±G% [% [ [ [% [ [