Interphase Tech 4538 MP3 Player User Manual


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The PCI Bridge
16 Interphase Corporation
PowerSpan Processor Bus Registers
These registers are used to define the parameters of the local to PCI windows. They are
mapped in the PCI memory space (base address defined in PCI configuration register 0x14
PCIBAR1) and in the local space for the local processor (base address 0xF0020000).
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Table 1-17. PowerSpan Processor Bus Registers
Offset Register Description
[ 3%B6,B&7/ 3URFHVVRU%XV6ODYH,PDJH&RQWURO5HJLVWHU
[ 3%B6,B7$''5 3URFHVVRU%XV6ODYH,PDJH7UDQVODWLRQ$GGUHVV5HJLVWHU
[ 3%B6,B%$''5 3URFHVVRU%XV6ODYH,PDJH%DVH$GGUHVV5HJLVWHU
[ 3%B6,B&7/ 3URFHVVRU%XV6ODYH,PDJH&RQWURO5HJLVWHU
[ 3%B6,B7$''5 3URFHVVRU%XV6ODYH,PDJH7UDQVODWLRQ$GGUHVV5HJLVWHU
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[ 3%B6,B&7/ 3URFHVVRU%XV6ODYH,PDJH&RQWURO5HJLVWHU
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[ 3%B6,B&7/ 3URFHVVRU%XV6ODYH,PDJH&RQWURO5HJLVWHU
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[ 3%B6,B%$''5 3URFHVVRU%XV6ODYH,PDJH%DVH$GGUHVV5HJLVWHU
  
[ 3%B6,B&7/ 3URFHVVRU%XV6ODYH,PDJH&RQWURO5HJLVWHU
[ 3%B6,B7$''5 3URFHVVRU%XV6ODYH,PDJH7UDQVODWLRQ$GGUHVV5HJLVWHU
[ 3%B6,B%$''5 3URFHVVRU%XV6ODYH,PDJH%DVH$GGUHVV5HJLVWHU
[ 3%B5(*B%$''5 3URFHVVRU%XV5HJLVWHU,PDJH%DVH$GGUHVV5HJLVWHU
[ 3%B&21)B,1)2 3URFHVVRU%XV3&,&RQILJXUDWLRQ&\FOH,QIRUPDWLRQ5HJLVWHU
[ 3%B&21)B'$7$ 3URFHVVRU%XV3&,&RQILJXUDWLRQ&\FOH'DWD5HJLVWHU
[$ 3%B3B,$&. 3URFHVVRU%XVWR3&,,QWHUUXSW$FNQRZOHGJH&\FOH5HJLVWHU
[% 3%B(55&6 3URFHVVRU%XV(UURU&RQWURODQG6WDWXV5HJLVWHU
[% 3%B$(55 3URFHVVRU%XV$GGUHVV(UURU/RJ5HJLVWHU
[& 3%B0,6&B&65 3URFHVVRU%XV0LVFHOODQHRXV&RQWURODQG6WDWXV5HJLVWHU
[' 3%B$5%B&75/ 3URFHVVRU%XV$UELWHU&RQWURO5HJLVWHU
Table 1-16. PowerSpan PCI Registers (cont)
Offset Register Description
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