Filter
Top Products
Chapter 1: Hardware Description
4538 Hardware Reference Manual 27
These devices keep their programming during power off. So the EPLD should normally be
already programmed and the normal user should not be aware of its programming.
The EPLDs are in a daisy-chain configuration, which enables all of them to be programmed
at once. They can be programmed in-situ by the PCI host, using some PowerSpan interrupts
as I/O pins. A jumper must be placed on board location JP1 to enable the programming
(when present, this jumper sets the ISP signal –ISPEN to its active state 0).
Serial EEPROM Connected to the PowerSpan
An I²C serial EEPROM is connected to the PowerSpan. It is used to store some PowerSpan
register initialization values and the PCI Vital Product Data (VPD). Other Interphase-
specific data is stored there, and there is still some room for other custom data. Table 1-22
shows the memory mapping for the EEPROM.
Details about the PowerSpan register initial load are described on Table 2-1 on page 60.
Additional information concerning Interphase-specific Production Data and Boot Monitor
parameters are provided in the 4538 Built-In Self Test and Monitor Manual. The VPD
and/or Custom Data is available space, for later use)
Board Equipment Register
The “Board Equipment Register” is a 32-bit word that allows the software to precisely
determine the board equipment. The first three bytes are common to several Interphase
Boards, so many field values are not possible on the 4538. For instance the 4538 does not
have Monarch capability, so the Monarch bit will always be set to 0.
Table 1-22. Serial EEPROM Mapping
Address Size Description
[±[) E\WHV 3RZHU6SDQUHJLVWHUVLQLWLDOORDG
[
±[ E\WHV %RDUG(TXLSPHQW5HJLVWHU
[
±[) E\WHV 93'DQGRU&XVWRPGDWD
[
±[$) E\WHV ,QWHUSKDVH6SHFLILF3URGXFWLRQ'DWD
[%
±[)) E\WHV %RRW0RQLWRUSDUDPHWHUV
Table 1-23. Board Equipment Register Layout
EEPROM
Offset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[ 03&B,' )/$6+B6,=( /6'5$0B6,=(
[ 6'5$0B6,=( &$0B6,=(
021$5&+
[ %86B)5(4
[ $&&(66