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Chapter 1: Hardware Description
4538 Hardware Reference Manual 33
Each line of the QuadFALC framers can be configured independently in Line Termination
mode (LT) or in Network Termination mode (NT). In the LT mode, the QuadFALC is in
slave mode and synchronizes on the lines. In the NT mode, the QuadFALC is in master
mode and synchronizes on a reference signal provided through connector P4 or on a free
running internal frequency.
On the front access board, the framers 1 and 2 are tied respectively to J1 and J2 connectors.
On the rear access board, the framers 1, 2, 3 and 4 are respectively tied to the lines 0, 1, 2
and 3 on P4 connector.
Additional details about the Infineon PEB22554 can be found at Infineon’s web site.
The Ethernet Transceiver
The Intel LXT971A is an IEEE compliant Fast Ethernet transceiver for 100-Base-TX and
10-Base-T applications. It is connected to the PowerQuicc II through a Media-Independent
Interface (MII). It features :
• 10-Base-T and 100-Base-TX
• Auto-Negotiation and Parallel Detection
• MII interface with extended register capability
• Robust baseline wander correction performance
• Standard CSMA/CD or Full-Duplex operation
• MDIO management interface
Its management interface is controlled by the PowerQuicc ports PC(25) (MDC) and PC(26)
(MDIO).
The LXT971A controls its own interrupt line to the local processor (-IRQ3).
The LXT971A reset input is controlled by the PowerQUICC II CPM I/O port PC(24)
(0=reset).
The LXT971A also includes three programmable LED drivers, which are used to control
the LEDs on the faceplate.
Table 1-29. Ethernet LEDs
LXT971
Output Description
/('&)* )DFHSODWH/('JUHHQ
/('&)* )DFHSODWH/('JUHHQ
/('&)* )DFHSODWH/('JUHHQ