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Chapter 3: Programming the Peripherals
4538 Hardware Reference Manual 73
Clocks and Baud-Rate Generators
Introduction
The CPM contains eight independent, identical, Baud-Rate Generators (BRGs) that can be
used with the FCCs, SCCs, and SMCs. The clocks produced by the BRGs are sent to the
bank-of-clocks selection logic, where they can be routed to the controllers. In addition, the
output of a BRG can be routed to a pin to be used externally.
BRGCLK
The BRGCLK is an internal signal generated in the MPC8260 clock synthesizer
specifically for the BRGs, the SPI, and the I
2
C internal BRG. BRGCLK is itself sourced
from VCO_OUT (twice the CPM clock) which is at 266.144 MHz. The DFBRG field of
SCCR must be programmed to 01, so that BRGCLK equals VCO_OUT/16 ( = 16.384
MHz). For more information on SCCR and DFBRG fields, see the MPC8260
PowerQUICC II Users Manual.
See Boot Firmware sources: app\asm\startup.asm.
BRG7 – TTY Baud-Rate Generator
The TTY interface is controlled by SMC1.
SMC1 baud-rate generator is BRG7.
Configure the CMXSMR register as follows:
• SMC1 = 0: SMC1 is not connected to TSA.
• Reserved = 0: This bit should be cleared.
• SMC1CS = 01: SMC1 transmit and receive clocks are BRG7.
• SMC2 = 0: SMC2 is not connected to TSA (don’t care).
• Reserved = 0: This bit should be cleared.
• SMC2CS = 00: SMC2 transmit and receive clocks are BRG2 (don’t care).
Final Result of CMXSMR register is 0x10. For more information on CMXSMR fields, see
the MPC8260 PowerQUICC II Users Manual.
The DIV16 field of BRGC7 register must be set to 0, so the first BRG7 divider will divided
the received BRGCLK clock by 1 and will use the 16.384 MHz clock.
To provide the proper baud-rate value (2400, 4800, 9600,... baud), the SMC1 clock source
must be 16 times the rate of the line (see BRGC7 register).
See Boot Firmware sources: app\c\montty.c - Function gwMonTTYOpen.
MCC Initialization
In Multiplexed Direct Mode and in Switched Mode, only MCCs TDMa1 is connected to
the framers. TDMa2, TDMbx, TDMcx, and TDMdx are not used. TDMa1 can transport up
to 128 MCC channels. This must be configured in the MCCF1 register.