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INTERNAL SPECIFICATIONS
77
Figure 4-7 Overall clock input control circuit for timer/counters 0 and 1
TIMER 1
GATE C/T M1 M0 GATE C/T M1 M0
76543210
TIMER MODE REGISTER (TMOD)
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
76543210
TIMER CONTROL REGISTER (TCON)
TIMER 0
DETECTOR
T1 PIN
(PORT 3.5)
DATA
INT1 PIN
(PORT 3.3)
LATCHS5
DETECTOR
T0 PIN
(PORT 3.4)
DATA
INT0 PIN
(PORT 3.2)
LATCHS5
XTAL 1 ÷12 S3
Q
Q