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MSM80C154S/83C154S/85C154HVS
210
5.10 Port Output Timing
1) One machine cycle instruction output timing
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
M1
S1
XTAL1
1
0
ALE
1
0
W-PORT
1
0
PORT-OUT
1
0
PORT NEW DATA
M1
PORT OLD DATA
1M CYCLE OP
INC data address
DEC data address
MOV data address, A
ORL data address, A
ANL data address, A
XRL data address, A
XCH A, data address
CPL bit address
CLR bit address
SETB bit address
Figure 5-15 One machine cycle instruction port output time chart