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CONTROL
47
Figure 3-6 Reset execution time chart (external ROM mode)
S1 S2 S3 S4 S5 S6
M1 or M2
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M2
S1 S2 S3 S4 S5 S6
M1
XTAL1
1
0
ALE
1
0
PSEN
1
0
PORT 0
1
0
PORT 1
1
0
PORT 2
1
0
PORT 3
1
0
RESET
1
0
CPU RESET
CONTROL
1
0
RESET
EXCECUTE
1
0
PORT DATA = 1
PORT DATA = 1
PORT DATA = 1
CPU RESET EXCECUTE CYCLE
S6
PCL
PCH PCH
FLOATING
PORT DATA
PORT DATA