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INPUT/OUTPUT PORTS
211
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
M1
S1
XTAL1
1
0
ALE
1
0
W-PORT
1
0
PORT-OUT
1
0
PORT NEW DATA
M2
PORT OLD DATA
2M CYCLE OP
MOV data address, # data
ORL data address, # data
ANL data address, # data
XRL data address, # data
JBC bit address, code address
POP data address
MOV data address, @Rr
MOV data address, Rr
MOV data address 1, data address 2
MOV bit address, C
2) Two machine cycle instruction output timing
Figure 5-16 Two machine cycle instruction port output time chart