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DESCRIPTION OF INSTRUCTIONS
239
Mnemonic
Instruction code
D7 D6 D5 D4 D3 D2 D1 D0
Byte Cycle Description Page
Classifi-
cation
Data transfer instructions
Bit manipu-
lation
instructions
Constant
value
instructions
CPL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOVC
MOVC
bit
A, Rr
A, direct
A, @Rr
Rr, A
Rr, direct
direct, A
direct, Rr
direct1,
direct 2
direct, @Rr
@Rr, A
@Rr, direct
A,@A+DPTR
A, @A+PC
2
1
2
1
1
2
2
2
3
2
1
2
1
1
1
1
1
1
1
2
1
2
2
2
1
2
2
2
(bit address)←(bit address)
(A)←(Rr) r=0~7
(A)←(direct address)
(A)←((Rr)) r=0 or 1
(Rr)←(A) r=0~7
(Rr)←(direct address) r=0~7
(direct address)←(A)
(direct address)←(Rr) r=0~7
(direct address 1)←(direct address 2)
(direct address)←((Rr)) r=0 or 1
((Rr))←(A) r=0 or 1
((Rr))←(direct address) r=0 or 1
(A)←((A)+(DPTR))
(PC)←(PC)+1
(A)←((A)+(PC))
277
316
317
315
321
322
326
327
328
325
312
313
329
330
10110010
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
11101r
2
r
1
r
0
11100101
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
1110011r
11111r
2
r
1
r
0
10101r
2
r
1
r
0
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
11110101
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
10001r
2
r
1
r
0
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
10000101
a
7
2
a
6
2
a
5
2
a
2
a
3
2
a
2
2
a
1
2
a
0
2
a
7
1
a
6
1
a
5
1
a
4
1
a
3
1
a
2
1
a
1
1
a
0
1
1000011r
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
1111011r
1010011r
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
10010011
10000011