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SYSTEM CONFIGURATION
35
2.10.2 Procedures and circuit connections used when external data memory (RAM)
is accessed by data pointer (DPTR)
The MSM80C154S/MSM83C154S can be connected to an external 64K word × 8-bit data
memory (RAM) when accessing the memory by data pointer (DPTR).
The data pointer (DPTR) consists of DPL and DPH registers. The DPL register contents serve
as addresses 0 thru 7 of the external data memory, and the DPH register contents serve as
addresses 8 thru 15.
The MOVX @DPTR, A instruction is used when accumulator contents are transferred to an
external data memory, and the MOVX A, @DPTR instruction is used when external data
memory contents are transferred to the accumulator. The external data memory connection
diagram is shown in Figure 2-26 and the external data memory access time chart is shown
in Figure 2-27.
When the data pointer indirect external memory instruction is executed, the CPU passes the
DPL register contents to port 0, and the port 0 contents are latched externally by ALE signal.
Data stored in the latch serves as the lower order addresses 0 thru 7 of the external data
memory (RAM), and the DPH register contents passed to port 2 serve as the higher order
addresses 8 thru 15 for addressing of the external data memory.
The WR or RD external data memory control signal is subsequently generated by the CPU
to enable transfer of data between port 0 and the external data memory.