Instruction Set Summay
4-205
Assembly Language Instructions
MSP50C614 (MSP50P614) IO Port Description
Address Bits Name R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 After RESET
0x34 4 DAC Control R/W DM E P1 P0 0x0
DM Drive Mode E Function P1 P0 DAC bits
0 3x Style DAC 0 Disable DAC 0 0 8 bit
1
5x Style DAC 1 Enable DAC 11
9 bits
0 10 bits
0x38 16 Interrupt
R/W CE AR PD EP E2 E1 S2 S1 D5 D4 PF D3 D2 T2 T1 DA 0x0000
General
Control
EP
F port Pull up
Timer Function Interrupt enable bits: 1=enable,0=disable
CE
Comparator
S1
Timer1 source
DA
DAC Timer interrupt
p
T2
Timer 2 interrupt
PD2 rising edge interr pt
0=disable 0 = MC
r
s
ng e
ge
nterrupt
p
1=enable 1 = MC
PF
F port falling edge interrupt
PD PDM clock E1 Timer1 enable
D4
PD4 rising edge interrupt
p
0
MC
E2 Timer2 enable
a
ng e
ge
n
errup
0 = disable
1 = enable
0x39 8 Interrupt
R/W D5 D4 PF D3 D2 T2 T1 DA left
ag
D5 PD5 fallin
ed
e interrupt fla
DA DAC Timer interrupt fla
unc
ange
D4
PD4 rising edge interrupt flag
T1
Timer 1 interrupt flag
D3
PD3 falling edge interrupt flag T2
Timer 2 interrupt flag
PF F port falling edge interrupt flag D2 PD2 rising edge interrupt flag
0x3A 16 Timer 1 period R/W T I M E R 1 P E R I O D 0x0000
0x3B 16 Timer 1 preset R/W T I M E R 1 P R E S E T 0x0000
0x3D 16 Clock
W T4 T3 T2 T1 T0 I C R M7 M6 M5 M4 M3 M2 M1 M0 0x0000
Speed
Control
Resistor Trim bits I
Idle bit
PLLM bits
=
(PLLM value+1) × 131.07 kHz
0 = disable
R
RTO
.
CPU clock = (PLLM value+1) × 65.536 kHz
1 = enable
0x3E 16 Timer 2 period R/W T I M E R 2 P E R I O D 0x0000
0x3F 16 Timer 2 preset R/W T I M E R 2 P R E S E T 0x0000
