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Cisco ONS 15310-MA SDH Reference Manual, Release 9.1 and Release 9.2
78-19417-01
Chapter 2 Card Reference
CE-100T-8 Card
Each 10/100 Ethernet port can be mapped to an SDH channel in increments of VC12 or VC3 granularity.
There are eight backend packet-over-SDH (POS) ports (VCAT groups [VCGs]) available on the
ML-100T-8 card. Additionally, the CE-100T-8 card supports packet processing, classification, quality of
service (QoS)-based queuing, and traffic scheduling.
Figure 2-3 shows the CE-100T-8 card faceplate and block diagram.
Figure 2-3 CE-100T-8 Faceplate and Block Diagram
The following paragraphs describe the general functions of the CE-100T-8 card and relate it to the block
diagram in Figure 2-3.
In the ingress direction (Ethernet-to-SDH), an octal PHY, which performs all of the physical layer
interface functions for 10/100-Mbps Ethernet, sends the frame to the packet processor for queuing in the
respective packet buffer memory. The packet processor performs packet processing, packet switching,
and classification. The Ethernet frames are then passed over SMII channels to the POS mappers, where
Ethernet traffic is terminated and is encapsulated using the PPP/HDLC or GFP framing protocols. The
encapsulation method is selected on a per-port basis. The encapsulated Ethernet frames are then mapped
into a configurable number of VCAT low-order and high-order payloads, such as VC12 synchronous
payload envelope (SPE), VC3 SPE, or a contiguous concatenated (CCAT) payload such as VC4 SPE. Up
to 63 VC12 SPEs or three VC3 SPEs can be virtually concatenated.
CE-100T-8
ACTIVE
LINK
1
ACT
LINK
2
ACT
LINK
3
ACT
LINK
4
ACT
LINK
5
ACT
LINK
7
ACT
LINK
6
ACT
LINK
8
ACT
Packet
Processor
(QoS
and
Queuing)
SMII
SMII
8 x
RJ45
8
622 Mbit
155 Mbit
155 Mbit
BTC48
8
Octal
PHY
POS
Mapper
and
VCAT/
LCAS
Engine
POS
Mapper
and
VCAT/
LCAS
Engine
Mux/
Demux
B
a
c
k
p
l
a
n
e
8
SMII
7
SMII
SMII
to MII
Adapter
MII
Intercard
Ethernet Links
PHY
CPU Complex
271811
