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S1D13504 Hardware Functional Specification
X19A-A-002-18 Issue Date: 01/01/30
Figure 7-24: Single Color 4-Bit Panel A.C. Timing
1. Ts = pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0])
2. t1
min
= t4
min
- 9Ts
3. t4
min
= [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] + 33 Ts
4. t5
min
= [((REG[04h] bits [6:0])+1)*8 - 1] Ts
5. t6
min
= [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts
6. t9
min
= [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
Table 7-21: Single Color 4-Bit Panel A.C. Timing
Symbol Parameter Min Typ Max Units
t1
FPFRAME setup to FPLINE falling edge
note 2
t2
FPFRAME hold from FPLINE falling edge
9 Ts (note 1)
t3
FPLINE pulse width
9Ts
t4
FPLINE period
note 3
t5
MOD transition to FPLINE falling edge
33 note 4 Ts
t6
FPSHIFT falling edge to FPLINE rising edge
note 5
t7
FPLINE falling edge to FPSHIFT falling edge
t14 + 0.5 Ts
t8
FPSHIFT period
1Ts
t9
FPSHIFT falling edge to FPLINE falling edge
note 6
t10
FPLINE falling edge to FPSHIFT rising edge
19 Ts
t11
FPSHIFT pulse width high
0.45 Ts
t12
FPSHIFT pulse width low
0.45 Ts
t13
UD[3:0], setup to FPSHIFT falling edge
0.45 Ts
t14
UD[3:0], hold from FPSHIFT falling edge
0.45 Ts
FPFRAME
FPLINE
MOD
Sync Timing
FPLINE
FPSHIFT
UD[3:0]
Data Timing
t5
t10
t1
t2
t4
t3
t7
t8
t12t11
t13
t14
1
2
t9
t6
