Epson S1D13504 Manual

A SERVICE OF

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Epson Research and Development Page 15

Vancouver Design Center

Interfacing to the Toshiba MIPS TX3912 Processor S1D13504

Issue Date: 01/02/02 X19A-G-012-04

Figure 5-1: S1D13504 to TX3912 Connection using One IT8368E

Note

For pin mapping see Table 3-1:, “Generic MPU Host Bus Interface Pin Mapping”.

IT8368E

S1D13504

A[12:0]

AB[12:0]

D[31:24]

DB[7:0]

LHA23/MFIO10

WE1#

WE0#

RD1#

RD0#

CS#

LHA22/MFIO9

LHA21/MFIO8

LHA20/MFIO7

LHA19/MFIO6

WAIT#

CARDxWAIT*

M/R#

RESET#

Latch

ALE

AB[20:13]

A23

TX3912

D[23:16]

DB[15:8]

DCLKOUT

Chip Select

Logic

Notes: The Chip Select Logic shown above is necessary to guarantee timing parameter t1

of the Generic MPU Interface Asynchronous Timing (for details refer to the

S1D13504 Hardware

Functional Specification

, document number X19A-A-002-xx).

ENDIAN

System RESET

BUSCLK

Oscillator

...or...

pull-up

V

DD

IO V

DD

, CORE V

DD

+3.3V

Clock divider

CLKI

See text

When connecting the S1D13504 RESET# pin, the system designer should be aware of all conditions

that amy reset the S1D13504 (e.g. CPU reset can be asserted during wake-up from power-down modes,

or during debug states).