S1D13504F00A Register Summary X19A-Q-001-03
Pa
e 1 01/02/02
Notes
1 n/a bits should be written 0.
reserved bits must be written 0
2 These bits are used to identify the S1D13504 at power on / RESET.
3 When using Little-Endian the RAMDAC should be connected to the low byte of the CPU data bus and the lower
register address given used. When using Big-Endian the RAMDAC should be connected to the high byte of the
CPU data bus and the higher register address given used.
4 DRAM Refresh Rate Select
5 Panel Data Width Selection
REG[00h] R
EVISION
C
ODE
R
EGISTER
2
R0
Product Code Revision Code
00000100
REG[01h] M
EMORY
C
ONFIGURATION
R
EGISTER
1/0 RW
n/a
1
Refresh Rate
4
n/a WE# Control n/a
FPM/EDO
Memory
Bit 2 Bit 1 Bit 0
REG[02h] P
ANEL
T
YPE
R
EGISTER
1/0 RW
n/a n/a
Panel Data Width
5
Panel Data
Format
Select
Color/Mono
Panel Select
Dual/Single
Panel Select
TFT/Passive
Panel Select
Bit 1 Bit 0
REG[03h] M
OD
R
ATE
R
EGISTER
RW
n/a n/a
MOD Rate
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[04h] H
ORIZONTAL
D
ISPLAY
W
IDTH
R
EGISTER
RW
n/a
Horizontal Display Width = 8(REG + 1)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[05h] H
ORIZONTAL
N
ON
-D
ISPLAY
P
ERIOD
R
EGISTER
RW
n/a n/a n/a
Horizontal Non-Display Period = 8(REG + 1)
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[06h] HRTC/FPLINE S
TART
P
OSITION
R
EGISTER
RW
n/a n/a n/a
HRTC/FPLINE Start Position = 8(REG + 1)
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[07h] HRTC/FPLINE P
ULSE
W
IDTH
R
EGISTER
RW
HRTC
Polarity
FPLINE
Polarity
n/a n/a
HRTC/FPLINE Pulse Width = 8(REG + 1)
Bit 3 Bit 2 Bit 1 Bit 0
REG[08h] V
ERTICAL
D
ISPLAY
H
EIGHT
R
EGISTER
0 RW
Vertical Display Height = (REG + 1)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[09h] V
ERTICAL
D
ISPLAY
H
EIGHT
R
EGISTER
1 RW
n/a n/a n/a n/a n/a n/a
Vertical Display Height
Bit 9 Bit 8
REG[0Ah] V
ERTICAL
N
ON
-D
ISPLAY
P
ERIOD
R
EGISTER
RW
VNDP
Status (RO)
n/a
Vertical Non-Display Period (VNDP) = (REG + 1)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Bh] VRTC/FPFRAME S
TART
P
OSITION
R
EGISTER
RW
n/a n/a
VRTC/FPFRAME Start Position = (REG + 1)
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Ch] VRTC/FPFRAME P
ULSE
W
IDTH
R
EGISTER
RW
VRTC
Polarity
FPFRAME
Polarity
n/a n/a n/a
VRTC/FPFRAME Pulse Width = (REG + 1)
Bit 2 Bit 1 Bit 0
REG[0Dh] D
ISPLAY
M
ODE
R
EGISTER
RW
n/a
Simultaneous Display
6
Option Select
Number Of Bits-Per-Pixel
7
CRT Enable LCD Enable
Bit 1 Bit 0 Bit 2 Bit 1 Bit 0
REG[0Eh] S
CREEN
1 L
INE
C
OMPARE
R
EGISTER
0 RW
Screen 1 Line Compare
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[0Fh] S
CREEN
1 L
INE
C
OMPARE
R
EGISTER
1 RW
n/a n/a n/a n/a n/a n/a
Screen 1 Line Compare
Bit 9 Bit 8
REG[10h] S
CREEN
1 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
0 RW
Screen 1 Display Start Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REG[11h] S
CREEN
1 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
1 RW
Screen 1 Display Start Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[12h] S
CREEN
1 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
2 RW
n/a n/a n/a n/a
Screen 1 Display Start Address
Bit 19 Bit 18 Bit 17 Bit 16
REG[13h] S
CREEN
2 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
0 RW
Screen 2 Display Start Address
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[14h] S
CREEN
2 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
1 RW
Screen 2 Display Start Address
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
REG[15h] S
CREEN
2 D
ISPLAY
S
TART
A
DDRESS
R
EGISTER
2 RW
n/a n/a n/a n/a
Screen 2 Display Start Address
Bit 19 Bit 18 Bit 17 Bit 16
REG[16h] M
EMORY
A
DDRESS
O
FFSET
R
EGISTER
0 RW
Memory Address Offset
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[17h] M
EMORY
A
DDRESS
O
FFSET
R
EGISTER
1 RW
n/a n/a n/a n/a n/a n/a
Memory Address Offset
Bit 9 Bit 8
REG[18h] P
IXEL
P
ANNING
R
EGISTER
RW
Screen 2 Pixel Panning Screen 1 Pixel Panning
Bit 3Bit 2Bit 1Bit 0Bit 3Bit 2Bit 1Bit 0
REG[19h] C
LOCK
C
ONFIGURATION
R
EGISTER
RW
n/a n/a n/a n/a n/a
MCLK
Divide
PCLK Divide
8
Bit 1 Bit 0
REG[1Ah] P
OWER
S
AVE
C
ONFIGURATION
R
EGISTER
RW
n/a n/a n/a n/a
LCD Power
Disable
Suspend Refresh Select
9
Software
Suspend
Bit 1 Bit 0
REG[1Bh] M
ISCELLANIOUS
D
ISABLE
R
EGISTER
RW
Host
Interface
Disable
n/a n/a n/a n/a n/a n/a
Half Frame
Buffer
Disable
REG[1Ch] MD C
ONFIGURATION
R
EADBACK
R
EGISTER
0 RO
MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status MD0 Status
REG[1Dh] MD C
ONFIGURATION
R
EADBACK
R
EGISTER
1 RO
MD15
Status
MD14
Status
MD13
Status
MD12
Status
MD11
Status
MD10
Status
MD9
Status
MD8
Status
REG[1Eh] G
ENERAL
IO P
INS
C
ONFIGURATION
R
EGISTER
0 RW
GPIO7 Pin
IO Config
GPIO6 Pin
IO Config
GPIO5 Pin
IO Config
GPIO4Pin
IO Config
GPIO3 Pin
IO Config
GPIO2 Pin
IO Config
GPIO1 Pin
IO Config
GPIO0 Pin
IO Config
REG[1Fh] G
ENERAL
IO P
INS
C
ONFIGURATION
R
EGISTER
1 RW
n/a n/a n/a n/a
GPIO11 Pin
IO Config
GPIO10 Pin
IO Config
GPIO9 Pin
IO Config
GPIO8 Pin
IO Config
REG[20h] G
ENERAL
IO P
INS
S
TATUS
/ C
ONTROL
R
EGISTER
0 RW
GPIO7 Pin
IO Status
GPIO6 Pin
IO Status
GPIO5 Pin
IO Status
GPIO4 Pin
IO Status
GPIO3 Pin
IO Status
GPIO2 Pin
IO Status
GPIO1 Pin
IO Status
GPIO0 Pin
IO Status
REG[21h] G
ENERAL
IO P
INS
S
TATUS
/ C
ONTROL
R
EGISTER
1 RW
GPO Control n/a n/a n/a
GPIO11 Pin
IO Status
GPIO10 Pin
IO Status
GPIO9 Pin
IO Status
GPIO8 Pin
IO Status
REG[22h] P
ERFORMANCE
E
NHANCEMENT
R
EGISTER
0 1/0 RW
EDO Read/
Write Delay
RC Timing
10
RAS# to
CAS# Delay
RAS# Precharge
11
Timing
n/a reserved
Bit 1 Bit 0 Bit 1 Bit 0
REG[23h] P
ERFORMANCE
E
NHANCEMENT
R
EGISTER
1 RW
Display FIFO
Disable
n/a n/a
Display FIFO Threshold
Bit 4Bit 3Bit 2Bit 1Bit 0
REG[24h] L
OOK
-U
P
T
ABLE
A
DDRESS
R
EGISTER
RW
n/a n/a
RGB Index Look-Up Table Address
Bit 1Bit 0Bit 3Bit 2Bit 1Bit 0
REG[26h] L
OOK
-U
P
T
ABLE
D
ATA
R
EGISTER
RW
n/a n/a n/a n/a
Look-Up Table Data
Bit 3Bit 2Bit 1Bit 0
REG[27h] L
OOK
-U
P
T
ABLE
B
ANK
S
ELECT
R
EGISTER
RW
n/a n/a
Red Bank Select Blue Bank Select Green Bank Select
Bit 1Bit 0Bit 1Bit 0Bit 1Bit 0
REG[28h]
OR
REG[29h]
3
RAMDAC P
IXEL
R
EAD
M
ASK
R
EGISTER
RW
RAMDAC Data
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Ah]
OR
REG[2Bh]
3
RAMDAC R
EAD
M
ODE
A
DDRESS
R
EGISTER
RW
RAMDAC Address
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Ch]
OR
REG[2Dh]
3
RAMDAC W
RITE
M
ODE
A
DDRESS
R
EGISTER
RW
RAMDAC Address
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
REG[2Eh]
OR
REG[2Fh]
3
RAMDAC P
ALETTE
D
ATA
R
EGISTER
RW
RAMDAC Data
Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Refresh Rate
Bits [2:0]
CLKI Divide Amount
Refresh Rate for 33MHz
CLKI
DRAM Refresh
Time/256 cycles
000 64 520 kHz 0.5 ms
001 128 260 kHz 1 ms
010 256 130 kHz 2 ms
011 512 65 kHz 4 ms
100 1024 33 kHz 8 ms
101 2048 16 kHz 16 ms
110 4096 8 kHz 32 ms
111 8192 4 kHz 64 ms
Panel Data Width Bits [1:0]
Passive LCD Panel Data
Width Size
TFT Panel Data Width
Size
00 4-bit 9-bit
01 8-bit 12-bit
10 16-bit 16-bit
11 Reserved Reserved
S1D13504F00A Register Summary
