Epson S1D13504 Manual

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Epson Research and Development Page 67

Vancouver Design Center

Hardware Functional Specification S1D13504

Issue Date: 01/01/30 X19A-A-002-18

7.4.4 Single Monochrome 8-Bit Panel Timing

Figure 7-21: Single Monochrome 8-Bit Panel Timing

VDP = Vertical Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1

VNDP = Vertical Non-Display Period = (REG[0Ah] bits [5:0]) + 1

HDP = Horizontal Display Period = ((REG[04h] bits [6:0]) + 1)*8Ts

HNDP = Horizontal Non-Display Period = ((REG[05h] bits [4:0]) + 1)*8Ts

HNDP

VDP

FPLINE

FPSHIFT

LINE1 LINE2 LINE3 LINE4 LINE479 LINE480

FPFRAME

LINE1 LINE2

FPLINE

MOD

1-2 1-10 1-634

1-3

1-11

1-635

1-4 1-12

1-636

1-5 1-13

1-637

1-6 1-14

1-638

1-7 1-15 1-639

1-8 1-16

1-640

1-1 1-9

1-633

MOD

VNDP

HDP

* Diagram drawn with 2 FPLINE vertical blank period

Example timing for a 640x480 panel

UD[3:0], LD[3:0]

UD2

UD1

UD0

UD3

LD2

LD1

LD0

LD3