Page 26 Epson Research and Development
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S1D13504 Programming Notes and Examples
X19A-G-002-07 Issue Date: 01/02/01
4.2.1 Registers
These three registers form the address of the word in the display buffer where screen 1 will start
displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on
the current color depth. Refer to the following table to see the minimum number of pixels affected
by a change of one to these registers.
The pixel panning register offers finer control over pixel pans than is available with the Start Address
Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending
on the current color depth certain bits of the pixel pan register are not used. The following table
shows this.
REG[10h] Screen 1 Display Start Address 0
Start Address
Bit 7
Start Address
Bit 6
Start Address
Bit 5
Start Address
Bit 4
Start Address
Bit 3
Start Address
Bit 2
Start Address
Bit 1
Start Address
Bit 0
REG[11h] Screen 1 Display Start Address 1
Start Address
Bit 15
Start Address
Bit 14
Start Address
Bit 13
Start Address
Bit 12
Start Address
Bit 11
Start Address
Bit 10
Start Address
Bit 9
Start Address
Bit 8
REG[12h] Screen 1 Display Start Address 2
n/a n/a n/a n/a
Start Address
Bit 19
Start Address
Bit 18
Start Address
Bit 17
Start Address
Bit 16
Table 4-1: Number of Pixels Panned Using Start Address
Color Depth (bpp) Pixels per Word Number of Pixels Panned
116 16
28 8
44 4
82 2
15 1 1
16 1 1
REG[18h] Pixel Panning Register
Screen 2
Pixel Pan
Bit 3
Screen 2
Pixel Pan
Bit 2
Screen 2
Pixel Pan
Bit 1
Screen 2
Pixel Pan
Bit 0
Screen 1
Pixel Pan
Bit 3
Screen 1
Pixel Pan
Bit 2
Screen 1
Pixel Pan
Bit 1
Screen 1
Pixel Pan
Bit 0
Table 4-2: Active Pixel Pan Bits
Color Depth (bpp) Pixel Pan bits used
1bits [3:0]
2bits [2:0]
4bits [1:0]
8bit 0
15/16 ---
