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INTERNAL SPECIFICATIONS
69
4.4.2.3 Timer control register (TCON)
TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Name Address
MSB LSB
76543210
Bit location Flag Function
TCON.0
TCON.1
TCON.2
TCON.3
TCON.4
TCON.5
TCON.6
TCON.7
IT0
IE0
IT1
IE1
TR0
TF0
TR1
TF1
External interrupt 0 signal used in level detect mode when this bit
is "0", and in trigger detect mode when "1".
Interrupt request flag for external interrupt 0.
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when IT0="1".
External interrupt 1 signal used in level detect mode when this bit
is "0",and in trigger detect mode when "1".
Interrupt request flag for external interrupt 1 .
Bit is reset automatically when interrupt is serviced.
Bit can be set and reset by software when IT1="1".
Counting start and stop control bit for timer/counter 0.
Timer/counter 0 starts counting when this bit is "1", and stops
counting when "0".
Interrupt request flag for timer interrupt 0.
Bit is reset automatically when interrupt is serviced. Bit is set to "1"
when carry signal is generated from timer/counter 0.
Counting start and stop control bit for timer/counter 1.
Timer/counter 1 starts counting when this bit is "1", and stops
counting when "0".
Interrupt request flag for timer interrupt 1 .
Bit is reset automatically when interrupt is serviced. Bit is set to "1"
when carry signal is generated from timer/counter 1.