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175
Figure 4-74 Restart from hard power down mode by reset (external ROM mode)
S1 S2 S3 S4 S5 S6
M1 → M2
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M1
XTAL1
1
0
ALE
1
0
PSEN
1
0
PORT 0
1
0
PORT 1
1
0
PORT 2
1
0
PORT 3
1
0
IOCON-bit 0
1
0
*RESET
1
0
EXECUTE CYCLERESET CYCLE
M1 → M2
CPU RESET
CONTROL
1
0
PORT DATA=1
PORT DATA=1
PORT DATA=1
FLOATING
PORT FLOATING
PORT FLOATING
PORT FLOATING
PORT FLOATING
HARD POWER DOWN MODE
HPDI[P3.5]
1
0
PCLPCLPCL
PCH PCH PCH
PCON-bit 6
1
0