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SYSTEM CONFIGURATION
37
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M2
S1 S2 S3 S4 S5 S6
M1
PCL PCL PCL PCL PCL PCLACC DATADPL
INSTRUCTION IN
PCH PCH PCH PCH DPH PCH PCH PCH
XTAL1
1
0
ALE
1
0
PSEN
1
0
WR
1
0
PORT–0
1
0
PORT–2
1
0
S6
PCL
MOVX @DPTR, A
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M2
S1 S2 S3 S4 S5 S6
M1
PCL PCL PCL PCL PCL PCLDPL
INSTRUCTION IN
PCH PCH PCH PCH DPH PCH PCH PCH
XTAL1
1
0
ALE
1
0
PSEN
1
0
RD
1
0
PORT–0
1
0
PORT–2
1
0
S6
PCL
MOVX A, @DPTR
RAM DATA IN
Figure 2-27 DPTR external data memory access timing