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INTERNAL SPECIFICATIONS
105
4.6.2.6 SERR
SERR is the status flag set when a framing error or overrun error is generated during UART
mode (mode 1, 2, or 3).
Framing error:
The SERR flag is set when no stop bit is detected in UART mode. Framing error is
detected irrespective of the data reception conditions set by SM2.
Overrun error:
The SERR flag is also set when the next data is ready to be transferred from the input
shift register to the SBUF which is already full in UART mode. Note that an overrun error
is only detected when the data reception conditions set by SM2 have been satisfied.
Although the SERR flag is set by hardware when a framing or overrun error is
generated, it is not an interrupt request flag. The flag must be checked by software to
determine whether it has been set or not. The flag must also be cleared by software.
Since the SERR flag is set by the logical OR of framing and overrun errors, it is not
possible to determine whether the error is a framing or overrun error simply by checking
the flag.
SERR is located at bit 5 of IOCON (I/O control register) specified by data address
0F8H. This bit can also be specified by bit address 0FDH.