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MZ-S1
3535
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. pF: µµF
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in Ω and
1
/
4
W or less unless otherwise
specified.
• % : indicates tolerance.
• C : panel designation.
• A : B+ Line.
• Total current is measured with MD installed.
• Power voltage is dc 3 V and fed with regulated dc power
supply from DC IN 3 V jack (J601).
• Voltages and waveforms are dc with respect to ground in
playback mode.
no mark : PLAYBACK
( ) : REC
〈〈 〉〉 : USB
∗
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 MΩ).
Voltage variations may be noted due to normal produc-
tion tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal produc-
tion tolerances.
• Circled numbers refer to waveforms.
• Signal path.
E : PLAYBACK
j : REC (ANALOG IN)
l : REC (DIGITAL IN)
F : USB CHECK OUT
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
form that of conventional IC.
6-4. NOTE FOR PRINTED WIRING BOARD AND SCHEMATIC DIAGRAMS
Note on Printed Wiring Board:
• X : parts extracted from the component side.
• Y : parts extracted from the conductor side.
• : Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from
(Conductor Side) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(Component Side) the parts face are indicated.
• MAIN board is four-layer printed board.
However, the patterns of layers 2 and 3 have not been
included in this diagrams.
• Lead Layouts
surfac
e
Lead layout of conventional IC CSP (chip size package)
Note: The components identified by mark 0 or dotted line
with mark 0 are critical for safety.
Replace only with part number specified.