SMSC LAN91C111 32/16/8-Bit Three-In-One Fast Ethernet Controller
Revision 1.0 (08-14-08) 60 SMSC AN 9.6
APPLICATION NOTE
10.2.17 Revision Register
The LAN91C111 chip ID and Revision register located in bank 3 at IO SPACE address 0x0A. The
chip ID is '9' and the revision is '1' for the LAN91C111. The software driver can read the Chip ID and
Revision Register to identify the 91C111 and enable the appropriate software support within the driver.
10.2.18 Physical Layer Address
The LAN91C111 internal Physical Layer (PHY) address is 00000. When the chip powers up, the
internal MII is disabled. Clearing the MII disable bit in the internal PHY Control Register can enable
the internal MII.
11 Design and Layout Check Guidelines
It is recommended to download and always refer to the latest updated LAN91C111 Data Sheet, the
SMSC reference design schematics, and other useful referring information which has all been posted
on the SMSC web site.
Please refer to SMSC web site---Ethernet Products---LAN Check Services, download the related
update guidelines of design and layout checking information for your general checking guidelines:
1. Schematics Checking List;
2. Layout Component Placement Check List;
3. Routing Check List;
4. Test Procedures;
5. EMI/ FCC Reduction Doc
