Major Chips Description 2-5
• Full Support for Advanced Configuration and Power Interface (ACPI) Revision 1.0
Specification and OS Directed Power Management
• Integrated IDE Controller
• Independent Timing of up to 4 Drives
• PIO Mode 4 and Bus Master IDE Transfers up to 14 Mbytes/sec
• Supports “Ultra DMA/33” Synchronous DMA Mode Transfers up to 33 Mbytes/sec
• Integrated 16 x 32-bit Buffer for IDE PCI Burst Transfers
• Supports Glue-less “Swap-Bay” Option with Full Electrical Isolation
• Enhanced DMA Controller
• Two 82C37 DMA Controllers
• Supports PCI DMA with 3 PC/PCI Channels and Distributed DMA Protocols
(Simultaneously)
• Fast Type-F DMA for Reduced PCI Bus Usage
• Interrupt Controller Based on Two 82C59
• 15 Interrupt Support
• Independently Programmable for Edge/Level Sensitivity
• Supports Optional I/O APIC
• Serial Interrupt Input
• Timers Based on 82C54
• System Timer, Refresh Request, Speaker Tone Output
• USB
• Two USB 1.0 Ports for Serial Transfers at 12 or 1.5 Mbit/sec
• Supports Legacy Keyboard and Mouse Software with USB-based Keyboard and Mouse
• Supports UHCI Design Guide
• SMBus
• Host Interface Allows CPU to Communicate Via SMBus
• Slave Interface Allows External SMBus Master to Control Resume Events
• Real-Time Clock
• 256-byte Battery-Back CMOS SRAM
• Includes Date Alarm
• Two 8-byte Lockout Ranges
• Microsoft Win95* Compliant
• 324 mBGA Package
